Laying chips vertically, instead of side by side, reduces the distance data has to travel by 1,000 times, making the chips faster and more efficient.
Big blue has said that it will start producing the compact silicon sandwiches in 2008.
Chip manufacturer Intel has previously announced that it is also developing similar vertical chip technology.
Last year, the firm unveiled a chip with 80 processing cores and capable of more than a trillion calculations per second (teraflops) that used vertical stacking technology.
Other firms, such as Tru-Si, have also developed techniques for creating 3D stacked chips.
High rise
Today most chips are laid out side-by-side, connected by wires.
The new technique involves placing chips directly on top of each other, connected by tungsten filled pipes, etched through the silicon.
These "through-silicon vias" (TSV), as they are known, eliminate the need for wires, increasing the speed at which information can flow between chips.
It has taken researchers at IBM a decade to refine the precise technique for mass producing the multi-storey chips.
"This allows us to move 3D chips from the 'lab to the fab' across a range of applications," said Lisa Su, vice president, semiconductor research and development center at IBM.
The first application will be in wireless communications chips. Using TSV will increase the efficiency of the chips by up to 40%, the firm says.
Speed boost
IBM is also exploring use of the technique in their multi-core chips.
As more and more cores are added to chips it becomes increasingly difficult to deliver uniform power to each one. By stacking them vertically and reducing the length of the connections between them, IBM hopes to overcome this problem,
Using these high-rise multi-core chips should also increase processor speeds and reduce power consumption.
Advantages like these also make 3D chips attractive for use in supercomputers.
IBM says it is developing the technology for use in the current fastest supercomputer in the world, Blue Gene/L.
The ultra powerful number cruncher, installed at the US Department of Energy's Lawrence Livermore National Laboratory (LLNL) is already capable of 280.6 trillions calculations per second.
The 3D stacked chips would allow a "new generation of supercomputers", IBM said.
The first chips will be available by the end of 2007 with full scale production expected to begin in 2008.
Comments